Program (Schedule)

Program in PDF format (printer friendly).

SSV2011 @ Kyoto Research Park, Nov. 1st, 2011
Time Assigned Speaker Affiliation Presentation Title
8:40 Open Registration Desk
9:00-9:05 Akira Fujimaki Nagoya University Opening Remarks
  Morning Session I (Chair : N. Yoshikawa)
9:05-9:45 Alex Kirichenko Hypres ERSFQ - Zero Static Power Dissipation RSFQ Logic (Invited)
9:45-10:25 Quentin Herr Northrop Grumman Ultra-Low-Power Superconductor RQL Logic (Invited)
  Coffee Break
  Morning Session II (Chair : A. Fujimaki)
10:50-11:15 Nobuyuki Yoshikawa Yokohama National University Development of Ultra-Low-Power Processors Using Adiabatic Quantum-Flux-Parametron Logic
11:15-11:40 Hirotaka Terai NICT Cryogenic Readout Technology Using SFQ Circuits for Large-Scale SNSPD Array (Invited)
11:40-12:05 Kazuyoshi Takagi Kyoto University Design Algorithms for Superconducting SFQ Logic Circuits
  Afternoon Session I (Chair : H. Myoren)
13:30-13:45 Hiroyuki Akaike Nagoya University Magnetic Effects of Fe3O4 Nanoparticle Films on SQUID Inductance
13:45-14:00 Akira Fujimaki Nagoya University Flux-Trap Suppression by Moats Formed in Nb and NbN Ground Planes
14:00-14:15 Yoshinao Mizugaki UEC Tokyo Quasi-Sine Waveform Synthesizer Based on SFQ Pulse-Frequency-Modulation
14:15-14:30 Yuki Yamanashi Yokohama National University High-Generation-Rate Superconductive Physical Random Number Generator Using Timing Jitter in Single Flux Quantum Circuit
14:30-14:45 Nobutaka Kito Kyoto University Timing-Aware Description Methods and Gate-Level Simulation of SFQ Logic Circuits
14:45-15:00 Hideaki Katayama Tohoku University Collective Switching Characteristics of Josephson Junctions
  Coffee Break
  Afternoon Session II (Chair : Y. Mizugaki)
15:25-15:40 Hiromi Matsuoka Nagoya University Gray Zone Widths of Quasi-One-Junction SQUIDs at High Frequencies
15:40-15:55 Hiroaki Myoren Saitama University SFQ Digital Signal Processing for Multi Quantum Beam Detector using STJ Array with Neutron Absorber
15:55-16:10 Kohei Ehara Yokohama National University Investigation of Wiring Methods to Supply Bias Currents to Serially Biased SFQ Circuits
16:10-16:25 Shuichi Nagasawa ISTEC Evaluation of Advanced Fabrication Process using both Diagnostic Chips and Shift Register Chips
16:25-16:40 Takahiro Kawaguchi Nagoya University Design of SFQ Circuits Using Clockless Logic Gates
16:40-16:45 Naofumi Takagi Kyoto University Closing Remarks

SSV 2011 sponsored by JST-CREST SFQ Project, MEXT SFQ Project, and JST-ALCA SFQ Project